1. Field of the Invention
The present invention relates to a damascene method for fabricating a metal interconnect, and more particularly, to a damascene method capable of avoiding copper extrusion.
2. Description of the Prior Art
In conventional integrated circuits, a metal interconnect is formed using aluminum and silicon dioxide. However, aluminum and silicon dioxide metal interconnects are not suitable for today's narrower line width and faster production speeds. Therefore, in recent years, the metal interconnect is formed with a damascene structure using copper and a dielectric material. The resistance of copper is approximately lower 40% than that of aluminum. The dielectric material can reduce the capacity effect of a metal conductive wire. Therefore, the damascene structure can decrease RC delay propagating when an electrical signal transmits and increase product performance.
A damascene method for fabricating the damascene structure mainly could be sub-classified into a method for fabricating a single damascene structure and a method for fabricating a dual damascene structure. Thereof, the method for fabricating a dual damascene is more complex, as shown in FIG. 1. At least one copper conductive wire 14 is formed on a base layer 10 such as an interlayer dielectric. Although not shown, the copper conductive wire 14 could electrically connect to another conductive area below the base layer 10 through the conductive plug 12. A first dielectric layer 20 is deposited on the copper conductive wire 14. A passivation 16 further would be formed between the conductive wire 14 and the first dielectric layer 20. A stop layer 22 is formed overlying the first dielectric layer 20. A second dielectric layer 24 is deposited on the stop layer 22. A hard mask 26 is formed on second dielectric layer 24. A dual damascene structure 30, exposing a portion of the copper conductive wire 14, is formed using the hard mask 26 to etch the first dielectric layer 20 and the second dielectric layer 24. A barrier layer 50 is deposited on the surface of the exposed copper conductive wire 14, the surface of the dual damascene structure 30, and the surface of the hard mask 26. A copper layer 52 is formed on the barrier layer 50.
The first dielectric layer 20 and the second dielectric layer 24 are dielectric materials having micro-vias, and an etching gas, like CF4, is used to etch the first dielectric layer 20 and the second dielectric layer 24 during fabrication of the dual damascene structure 30. As a result, some of the etching gas remains in the micro-vias, preventing the barrier layer 50 from being deposited effectively on the first dielectric layer 20 and the second dielectric layer 24. As a consequence of the etching gas remaining in the micro-vias, there may be small gaps in the barrier layer 50 or the barrier layer 50 may be incompletely formed in the areas of the remaining gas. In this situation, the subsequently formed copper layer 52 effuses out through the barrier layer 50 to form the defect of copper extrusion, as indicated by numeral 70.